Marvell Computex 2026 Keynote. Key Takeaways & Full Transcript
Event: Computex 2026 opening keynote (Day One)
Speaker: Matt Murphy, Chairman and CEO, Marvell Technology
Guests on stage: Jensen Huang (CEO, NVIDIA); Dr. Tien Wu (CEO, ASE / Advanced Semiconductor Engineering)
Summary date: June 2, 2026
Executive Summary
Matt Murphy framed the keynote around a single question, “What defines the performance of AI infrastructure?”, and argued the answer is connectivity rather than compute or memory alone. His stated thesis: modern AI workloads require tens of thousands, and eventually millions, of processors operating as one engine, making AI scaling “fundamentally a connectivity challenge.” He described connectivity as the next bottleneck after compute (which he tied to NVIDIA) and memory, and said the shift from copper to optical interconnect is happening now.
Murphy recapped a decade-long transformation since he became CEO in 2016, repositioning Marvell from a consumer-weighted chipmaker (more than 60% consumer revenue in 2016) into a data-infrastructure pure-play. He cited, as separate figures, roughly $36 billion invested in the platform overall, about $22.5 billion of that via acquisitions (including Inphi for $10 billion, plus Cavium, Avera, Aquantia, Innovium, and, per his remarks, the recent Celestial AI and XConn acquisitions), about $18 billion spent organically, and about $4.5 billion of assets divested. He said data center now represents over 75% of revenue, versus under 10% at the start.
On finances, Murphy cited Marvell’s reported growth and forward Wall Street consensus (not guidance): roughly $2.3 billion in 2016, scaling toward an approximately $11.4 billion consensus current-year figure and an approximately $16.4 billion consensus the following year, with recent growth near 40% per year. (Marvell’s last reported full fiscal year, FY2026 ended January 31, 2026, was $8.195 billion of revenue per its SEC filing.)
He positioned Marvell as the “undisputed connectivity leader” and “the Switzerland of the industry,” with the most complete portfolio “from millimeters to kilometers,” spanning coherent optics between data centers, PAM-4 and Ethernet switching inside data centers, copper SerDes inside the rack, and die-to-die interfaces inside the package. He introduced the “copper wall” concept: as per-lane speeds rise, copper reach shrinks (about 2.5 meters at 200 Gbps), pushing optics, including co-packaged optics (CPO), inside the rack.
Key announcements: a 100T Ethernet switch (stated industry-lowest power); a “world’s first” 1.6-terabit, 2nm coherent optical solution to sample later this year; a 51.2T CPO switch (16 × 3.2T optical engines) shown on stage; and a restated $2 billion NVIDIA investment plus an expanded partnership across optics, photonics, and NVLink Fusion.
Jensen Huang said “useful AI has arrived” and is now profitable, detailed NVIDIA’s Hopper-to-Vera-Rubin roadmap and NVLink Fusion’s role in disaggregated data centers, and summarized the interconnect strategy as “use copper wherever you can, use optics wherever you must.” Dr. Tien Wu described ASE’s early bet on Marvell and Taiwan’s hard-to-replicate semiconductor ecosystem. Murphy closed with a “data center without distance” vision in which optical interconnect enables fully disaggregated, dynamically composed systems.
Let’s dig in…
